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Development Of A Hardware In The Loop Test Setup Based On System On Chip Board

BROWSE_DETAIL_CREATION_DATE: 22-12-2017

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BROWSE_DETAIL_TYPE: Thesis

BROWSE_DETAIL_SUB_TYPE: Masters

BROWSE_DETAIL_PUBLISH_STATE: Unpublished

BROWSE_DETAIL_FORMAT: PDF Document

BROWSE_DETAIL_LANG: English

BROWSE_DETAIL_SUBJECTS: Electrical engineering. Electronics. Nuclear engineering,

BROWSE_DETAIL_CREATORS: Shwehdi, Rabei Abdulhafid S. (Author),

BROWSE_DETAIL_CONTRIBUTERS: Özbek, Mehmet Efe (Advisor),

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HIL simulation, Model based design


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This thesis proposed a hardware in the loop (HIL) test setup based on system on chip board (SoC) board, that can be used for testing a plant model developed using Simulink HDL coder and Xilinx System Generator (XSG) library. The plant model was converted to Verilog code using XSG system generator and uploaded to SoC board using Vivado Design Suite. The programmed SoC board was interfaced to real input signals through analog to digital converters (ADC) and the output signal of plant was carried to the measurement device through a digital to analog converter (DAC). Drivers, in the form XSG models, were developed for ADC and DAC modules which implement the communication protocols of the modules to achieve data transmission between these modules and the SoC board. The operation of the HIL setup has been verified for a simple plant model.


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