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Implementation Of Matched Filter For Radar Receiver On Fpga

Oluşturulma Tarihi: 15-11-2018

Niteleme Bilgileri

Tür: Tez

Alt Tür: Yüksek Lisans Tezi

Yayınlanma Durumu: Yayınlanmamış

Dosya Biçimi: PDF

Dil: İngilizce

Konu(lar): Elektrik mühendisliği. Elektronik. Nükleer mühendislik,

Yazar(lar): Shfat, Mohamed Salem A. (Yazar),

Emeği Geçen(ler): Özbek, Mehmet Efe (Danışman),

Anahtar Kelimeler

Radar systems and receiver, Matched Filter, FPGA, Verilog HDL


Özet

The underlying thesis scouts about a radar receiver in general and the Matched Filter and the implementation of this filter on the field programmable gate array FPGA. The practical implementation of the radar system is not as simple as its basic concept might seem. The Radar is operated by detection of the echo which is returned from reflecting objects (targets) and radiating the electromagnetic energy.The information about the target is provided by the nature of the echo signal such as position, velocity, and perhaps size. Several sources exist which are able to affect and confuse the quality of the radar these include undesired interference and echo The Matched Filter is a kind of filter helps to separate the reflected signal from the clutters and undesired echoes by increasing the SNR of the received echo in order to give the radar high ability to detect the targets successfully. The FPGA have been chosen as a platform for this work because of its high quality and speed in processing especially in digital systems design. In this work, the Matched filter is implemented on FPGA by using the Verilog language and MATLAB for generating the echo signals. Throughout this study, it was clearly shown that all the selected tools and language are suitable for this practical work.


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